openTPU releases a full toolchain for running models on an FPGA

The project offers a learning example combining real FPGA execution with the complete accelerator toolchain.

Jaeyong KimOct 7, 2026Technology

openTPU is an AI-accelerator project releasing RTL, an instruction set, a simulator and a compiler that the developer says were built with AI assistance. The developer reports running several small models on a Kintex-7 FPGA card, with generated tokens matching the simulator in some tests. Public compiler documentation says Python kernels are lowered into instructions while data placement and movement must be specified explicitly. This is not yet a mass-production achievement for a custom chip or an independent performance validation.

Sources

FeSens/openTPU: An open-source AI accelerator, developed by AI: RTL, ISA, simulator, compiler and profiler in one repo. Runs Qwen3, LFM2.5 and Qwen3.5 on a Kintex-7 PCIe card. — GitHub
openTPU/docs/compiler.md at main — FeSens/openTPU — GitHub